1. Field of the Invention
The present invention relates to peripheral devices in computer systems, and more particularly to a processor with an internal register for maintaining status information for peripheral devices in a computer system.
2. Related Art
Computer systems typically include a central processing unit that is coupled to and communicates with a plurality of peripheral devices, typically through a computer system bus. These peripheral devices can include: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller. A peripheral device frequently requires attention from the central processing unit in order to transfer data between the central processing unit and the peripheral device, or to otherwise command and manipulate the peripheral device. This attention is typically triggered by an interrupt, which the peripheral device sends to the central processing unit on order to xe2x80x9cinterruptxe2x80x9d normal processing by the central processing unit. During an interrupt, the central processing unit temporarily suspends normal processing and executes a piece of code known as an xe2x80x9cinterrupt service routinexe2x80x9d to perform the required service for the peripheral device. Once the interrupt service routine is complete, the central processing unit resumes normal processing.
Many computer systems use a shared interrupt architecture, in which a plurality of peripheral devices can activate the same interrupt signal. One commonly-used shared interrupt architecture is a daisy-chained structure, in which peripheral devices are xe2x80x9cchainedxe2x80x9d together through one or more interrupt lines. Any peripheral device in the chain can generate an interrupt signal, and this interrupt signal is passed through the chain until it ultimately reaches the central processing unit. In another commonly-used shared interrupt architecture, peripheral devices share a common interrupt bus line; peripheral devices can signal an interrupt to the processor by asserting this interrupt bus line.
A shared interrupt architecture has certain advantages. It is very simple; typically requiring only a small number of signal lines to carry interrupt signals. It is also expandable, typically allowing additional peripheral devices to be integrated into a computer system without requiring additional lines for interrupt signals.
However, a shared interrupt architecture suffers from a major disadvantage. It requires the central processing unit to determine which peripheral device requires processing. This is because all of the peripheral devices generate the same interrupt signal, and the central processing unit cannot tell from the interrupt signal which peripheral devices require servicing. Hence, the central processing unit must typically xe2x80x9cpollxe2x80x9d the peripheral devices in order to determine which peripheral devices require servicing.
This polling process can be quite time-consuming. The central processing unit may have to poll every peripheral device in the computer system, even though only one peripheral device typically requires servicing at any given time. Polling reduces CPU efficiency, because the CPU must perform multiple bus transactions to poll the peripheral devices, and each bus transaction can require a large number of CPU cycles in a high performance computing system. Polling also ties up the peripheral bus with a large number of polling accesses. Furthermore, polling increases the time required for servicing an interrupt. This may create problems for peripheral devices that require servicing in a timely manner. For example, a network interface controller may require immediate servicing to prevent a buffer of incoming data from overflowing. This immediate servicing may be delayed by polling.
What is needed is a system for retrieving status information from peripheral devices in a shared interrupt architecture that reduces the amount of time and bus activity required to determine the status of the peripheral devices.
One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the CPU. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register. This apparatus includes a communication channel coupled to a central processing unit and a number of peripheral devices. A status register is coupled with the central processing unit to store status information for the peripheral devices. An updating circuit is located within the core logic unit and is coupled between the communication channel and the status register. This updating circuit includes a mechanism to update the status register in response to signals containing status information received from the peripheral devices through the communication channel.
Another embodiment of the present invention includes a special-purpose processor instruction that reads the status register and automatically branches to the appropriate interrupt service routine based upon the contents of the status register.
In another embodiment of the present invention, the communication channel includes a computer system bus. In a variation on this embodiment, the communication channel includes a processor-to-memory bus. In a further variation on this embodiment, the communication channel carries signals for maintaining coherency between multiple caches in the computer system.
In another embodiment of the present invention, the computer system includes a plurality of central processing units and a plurality of status registers coupled between the central processing units and the communication channel.
In another embodiment of the present invention, the computer system includes a wire-ORed interrupt structure that couples the peripheral devices to the central processing unit through a core logic unit
Another embodiment of the present invention can be characterized as an apparatus within a processor for updating a status register to indicate changes in the status of peripheral devices in a computer system. This apparatus includes a plurality of address inputs coupled to address lines of a bus, wherein the bus is coupled to the peripheral devices. This apparatus also includes an address detecting circuit coupled to a set of higher order bits in the plurality of address inputs. This address detecting circuit is configured to detect an address in a reserved range of addresses specified by the set of higher order bits. The apparatus additionally includes a decoder circuit coupled to a set of lower order bits in the plurality of address inputs. This decoder circuit detects references to particular addresses in the reserved range of addresses. A status register is coupled to a set of outputs from the decoder circuit, so that a reference to a particular address in the reserved range of addresses by a peripheral device feeds through the decoder and updates status information for the peripheral device in the status register. The status register also includes outputs coupled to a central processing unit so that the status register can be read by the central processing unit.
In a variation on this embodiment, the address detecting circuit includes a decoder. In another variation, the address detecting circuit includes a comparator.